LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY trail1 IS
	PORT(
		CLK: IN STD_LOGIC;
		Q:	  OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END trail1;

ARCHITECTURE BHV OF trail1 IS 
	SIGNAL Q1: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK = '1' THEN 
		Q1 <= Q1 + 1;
		END IF;
	END PROCESS;
	Q<=Q1;
END BHV;
	